1. Field of the Invention
This invention relates to contact resistance of butted contacts in semiconductor memory devices and more particularly to butted contacts in SRAM devices.
2. Description of Related Art
It is difficult to reduce butted contact resistance in sub-half micron SRAM devices because of Si/Si or Si/WSix interfaces. A high resistance node sometimes acts to contribute to killing the yield of a manufacturing process.
U.S. Pat. No. 5,607,881 of Huang for "Method of Reducing Buried Contact Resistance in SRAM" shows an extra ion implant into a trench but not into the polysilicon. A buried contact is formed within a semiconductor substrate by dopant diffusion from an overlying polysilicon layer. The second polysilicon layer is patterned to form a polysilicon contact overlying the buried contact junction wherein a portion of the buried contact within said semiconductor substrate is exposed. The polysilicon layer is overetched whereby a trench is etched into the exposed semiconductor substrate. An extra implant is implanted into the semiconductor substrate around the trench.
U.S. Pat. No. 5,393,687 of Liang for "Method of Making Buried Contact Module with Multiple Poly Si Layers" teaches a method of making buried contact module with multiple polysilicon layers.
U.S. Pat. No. 5,596,215 of Huang for "Method to Improve Buried Contact Resistance" teaches a method for filling a conductive trench in a buried contact.
U.S. Pat. No. 5,668,051 of Chen et al for "Method of Forming Poly Plug to Reduce Buried Contact Resistance" describes driving dopant from a second polysilicon layer to form a buried contact junction and etching away the second polysilicon layer where a planned source/drain region will be formed adjacent to the buried contact junction.
An object of this invention is to reduce butted contact resistance because of lower resistivity in the contact area.